Cyberlabo DDR SDRAM Simulation Model in VHDL

○ Supply source codes, You can copy in your site.!!

○ Fast simulation with the dynamic memory allocation technique!!

○ Written in VHDL only. No other software is requiered for simulation.
 

○ Enable precise functional check
                 Timing violation detect
                  Read/Write access check
                  Refresh rate check

○ And  ...       Reasonable price!!
 
 

● Data initialize file read
● Data dump to a file with signal trigger
                 Dump out all accessed address and current data at an arbitorary time
 

Cyberlabo Limited   TEL 0427-39-7756   FAX　0427-39-7757

Machida office:  1-9-5, Naka-machi, Machida, Tokyo, Japan            194-0021
Headquarter :     4-15, Wakamatsu-cho, Hadano, Kanagawa, Japan     259-1314
 

mailto: webmaster@cyber-labo.co..jp