VHDL Models

Last modified 15 Apr. 2004

CPU Core Model - VLP80 (Variable Length instruction Processor 80)

Our 16/32 bit Z80 binary compatible RISC CPU core model. Pipelined architecture executes commands in fewer clock cycles. It can execute Z80 commands at 20-40 MIPS.
Please contact us for more details.

PCI Core Model

PCI initiator model
Behaivior model for PCI Target debug.Any access type is avairable.it's contoroled by external file.No VHDL analyze required when you modified data or address.

These cores are semi-custom model for synthesys.
PCI bridge VHDL model
PCI-PCI bridge(32-32,64-64,32-64), user sepcific
SDRAM controller with PCI interface VHDL model
SDRAM contoroller for GIGA byte class memory system.

VITAL DRAM Simulatiom Model

We have available the following original VHDL simulation models.

All models feature :

Pure VHDL code.(C code is not included)Fit for any VHDL simulator
Variable address size and Data Bus size.
VITAL timing and functions.
Capability to simulate any vendor's DRAM with adjustment of delay parameters.
Complete simulation model including refresh simulation.

Follow the following links for more information :

EDO-DRAM simulation model EDO DRAM VHDL Model

Synchronous DRAM simulation model Synchronous DRAM VHDL Model

Synchronous Graphics DRAM simulation model Synchronous Graphics DRAM VHDL Model

DDRSDRAM simulation model Double Data Rate Synchronous DRAM VHDL Model

User Specific Model:

We also are happy to make models meeting the specific needs of a customer - (synthesizable or behavioural models).

Ask webmaster@cyber-labo.co.jp

Free VHDL Models

Free VHDL models
We do not provide user support for these free models. Comments are included in source code though.

question and commentwebmaster@cyber-labo.co.jp

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